PCI configuration registers:
  Common header:
    0x00: 0x14511022 0x00100004 0x08060000 0x00800000

    Vendor Name: AMD (0x1022)
    Device ID: 0x1451
    Command register: 0x0004
      I/O space accesses: off
      Memory space accesses: off
      Bus mastering: on
      Special cycles: off
      MWI transactions: off
      Palette snooping: off
      Parity error checking: off
      Address/data stepping: off
      System error (SERR): off
      Fast back-to-back transactions: off
      Interrupt disable: off
    Status register: 0x0010
      Immediate Readiness: off
      Interrupt status: inactive
      Capability List support: on
      66 MHz capable: off
      User Definable Features (UDF) support: off
      Fast back-to-back capable: off
      Data parity error detected: off
      DEVSEL timing: fast (0x0)
      Slave signaled Target Abort: off
      Master received Target Abort: off
      Master received Master Abort: off
      Asserted System Error (SERR): off
      Parity error detected: off
    Class Name: system (0x08)
    Subclass Name: IOMMU (0x06)
    Interface: 0x00
    Revision ID: 0x00
    BIST: 0x00
    Header Type: 0x00+multifunction (0x80)
    Latency Timer: 0x00
    Cache Line Size: 0bytes (0x00)

  Type 0 ("normal" device) header:
    0x10: 0x00000000 0x00000000 0x00000000 0x00000000
    0x20: 0x00000000 0x00000000 0x00000000 0x87471043
    0x30: 0x00000000 0x00000040 0x00000000 0x000001ff

    Base address register at 0x10
      not implemented
    Base address register at 0x14
      not implemented
    Base address register at 0x18
      not implemented
    Base address register at 0x1c
      not implemented
    Base address register at 0x20
      not implemented
    Base address register at 0x24
      not implemented
    Cardbus CIS Pointer: 0x00000000
    Subsystem vendor ID: 0x1043
    Subsystem ID: 0x8747
    Expansion ROM Base Address: 0x00000000
    Capability list pointer: 0x40
    Reserved @ 0x38: 0x00000000
    Maximum Latency: 0x00
    Minimum Grant: 0x00
    Interrupt pin: 0x01 (pin A)
    Interrupt line: 0xff

  Capability register at 0x40
    type: 0x0f (Secure Device)
  Capability register at 0x64
    type: 0x05 (MSI)
  Capability register at 0x74
    type: 0x08 (HyperTransport)

  PCI Message Signaled Interrupt
    Message Control register: 0x0084
      MSI Enabled: off
      Multiple Message Capable: yes (4 vectors)
      Multiple Message Enabled: off (1 vector)
      64 Bit Address Capable: on
      Per-Vector Masking Capable: off
      Extended Message Data Capable: off
      Extended Message Data Enable: off
    Message Address (lower) register: 0x00000000
    Message Address (upper) register: 0x00000000
    Message Data register: 0x0000

  HyperTransport Capability Register at 0x74
    Command register: 0xa803
      Capability Type: 0x15 (MSI Mapping)
      Enable: on
      Fixed: on
    Address Low register: 0x87471043
    Address high register: 0x00002b01
      Address: 0x00002b0187400000

  Device-dependent header:
    0x40: 0x190b640f 0xfeb80001 0x00000000 0x00000000
    0x50: 0x00203040 0x00000080 0x00000000 0x00000000
    0x60: 0x00000000 0x00847405 0x00000000 0x00000000
    0x70: 0x00000000 0xa8030008 0x87471043 0x00002b01
    0x80: 0x62201ada 0x0003cfcf 0x00000000 0x00000000
    0x90: 0x00000000 0x00000000 0x00000002 0x00000000
    0xa0: 0x00000000 0x2c0007bf 0x0e739c10 0x00000000
    0xb0: 0x00000000 0x00000000 0x00000075 0x00000000
    0xc0: 0x00000000 0x00000000 0x00000000 0x00000000
    0xd0: 0x00000000 0x00000000 0x00000000 0x00000000
    0xe0: 0x00000000 0x00000000 0x00000000 0x00000000
    0xf0: 0x00000000 0xffffffff 0x00000000 0xffffffff